NVIDIA RTX 4070 SUPER has at least more L2 cache
The company made a mistake during the official launch presentation.
The RTX 4070 SUPER has not 36 MB, but 48 MB of L2 cache available. NVIDIA made a mistake in the official specifications announced during the official launch presentation. The error has not yet been corrected.
Four new maps were announced for desktop gamers at CES 2024. AMD has launched its Radeon RX 7600 XT GPU for the mid-range segment at $329, while NVIDIA is focusing on models priced at least twice that and launching the RTX 4070 SUPER at $599. This model replaces the current RTX 4070, which is now discounted to $549.
Official specifications listed in the test guide show an L2 cache size of 36MB for the RTX 4070 SUPER model. This information was also included in the official marketing slide. However, NVIDIA has now updated the specifications to say that this model actually uses 48MB of L2 cache. No further changes were reported.
The size of the L2 cache plays an important role in the memory subsystem of the Ada Lovelace GPU architecture. This factor can limit VRAM pool requests, which is especially important for cards with limited 128-bit RTX 4060 series memory buses. For the RTX 40 series, NVIDIA has updated the L2 cache size for all of its consumer GPUs, improving to 96MB of L2 cache on the AD102 and 32MB on the AD107/106.
The AD104, on which the RTX 4070 series is based, has 48MB of total L2 cache. Since the RTX 4070 SUPER uses an AD104 GPU with the multi-SMS feature enabled (56 out of 60), it doesn’t make sense for NVIDIA to limit it to 36MB, which is also the original RTX 4070 specification.
With this in mind, the RTX 4070 SUPER will undoubtedly show a noticeable improvement in gaming with 20% more cores and 33% more L2 cache. However, reference-spec models may be limited to a standard TDP of 220W, which is only 20W more than the RTX 4070.
The RTX 4070 SUPER is scheduled to hit the market on January 17, with the first test reports coming a day earlier.
Nvidia GeForce RTX 40 | ||||
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videocardz.com | Short message | Coda core | See memory bus | L2-cache |
M102 | ||||
M103 | ||||
M104 | ||||
M106 | ||||
M107 |